--******************************************************************************
-- File: SVGA_DEFINES_vhdl.vhd
-- Author: Matthew Hosking
-- Created: 09/01/2009
-- Description: Mimics the defined values in SVGA_DEFINES.v except this is used
--				and referenced by the VHDL components. The Verilog version has
--				multiple configurations available and this VHDL file only
--				lists the necessary setting to use basic VGA.
--******************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.all;

--******************************************************************************
-- Package Declaration
--
--		**Copied from Xilinx SVGA_DEFINES.v:
--		To select a resolution and refresh rate, remove the comments around the 
--		desired block in this file. The pixel clock output by the DCM module 
--		should approximately equal the rate specified above the timing block 
--		that is uncommented.
--******************************************************************************
package SVGA_DEFINES_vhdl is
	--DEFINE THE VARIOUS PIPELINE DELAYS
	constant CHARACTER_DECODE_DELAY : integer := 4;
	--------------------------------------------------------
	-- 640 X 480 @ 60Hz with a 25.175MHz pixel clock
	--------------------------------------------------------	
	constant H_ACTIVE			: integer := 640;	--pixels
	constant H_FRONT_PORCH 	: integer := 16;	--pixels
	constant H_SYNCH			: integer := 96;	--pixels
	constant H_BACK_PORCH	: integer := 48;	--pixels
	constant H_TOTAL			: integer := 800;	--pixels

	constant V_ACTIVE			: integer := 480;	--lines
	constant V_FRONT_PORCH 	: integer := 11;	--lines
	constant V_SYNCH			: integer := 2;	--lines
	constant V_BACK_PORCH	: integer := 31;	--lines
	constant V_TOTAL			: integer := 524;	--lines
	
	constant CLK_MULTIPLY	: integer := 2;	--100 * 2/8 = 25.000 MHz
	constant CLK_DIVIDE	 	: integer := 8;
	
	--------------------------------------------------------
	-- 800 X 600 @ 60Hz with a 40.000MHz pixel clock
	--------------------------------------------------------	
	--	constant H_ACTIVE			: integer := 800;	--pixels
	--	constant H_FRONT_PORCH 	: integer := 40;	--pixels
	--	constant H_SYNCH			: integer := 128;	--pixels
	--	constant H_BACK_PORCH	: integer := 88;	--pixels
	--	constant H_TOTAL			: integer := 1056;--pixels
	--
	--	constant V_ACTIVE			: integer := 600;	--lines
	--	constant V_FRONT_PORCH 	: integer := 1;	--lines
	--	constant V_SYNCH			: integer := 4;	--lines
	--	constant V_BACK_PORCH	: integer := 23;	--lines
	--	constant V_TOTAL			: integer := 628;	--lines
	--	
	--	constant CLK_MULTIPLY	: integer := 2;	--100 * 2/5 = 40.000 MHz
	--	constant CLK_DIVIDE	 	: integer := 5;
end SVGA_DEFINES_vhdl;